1. Field of the invention
This invention relates in general to a semiconductor memory device and, more particularly, to a semiconductor memory device which is improved for increasing the storage capacity. It also relates to a method for producing the semiconductor memory device.
2. Description of the Prior Art
An IC memory is made up of a memory cell array composed of a large number of storage elements and input/output peripheral circuits. In many cases, these elements and peripheral circuits are formed on one and the same substrate.
FIG. 5 is a block diagram showing an example of a conventional RAM. Referring to this figure, a plurality of word lines and a plurality of bit lines are arranged in a memory cell 1 for intersecting each other. A memory cell is provided at each point of intersection between these word and bit lines. Selection of a memory cell is attained on the basis of a point of intersection between a word line selected by an X address buffer decoder 2 and and a bit line selected by a Y address buffer decoder 3. Data and written into or read out from the selected memory cell. Data write/read commands are issued by read/write (R/W) control signals supplied from a read/write control circuit 4. During data writing input data (Din) are entered in the selected memory cell via R/W control circuit 4. During data reading, data stored in the selected memory cell are sensed by a sense amplifier 5, amplified and outputted via a data output buffer 6 as to the output data (Dout).
FIG. 6 is an equivalent circuit diagram of a dynamic memory cell for illustrating the write/read operation for a memory cell.
Referring to this figure, the dynamic memory cell includes a set of a field effect transistor 7 and a capacitor 8. The field effect transistor 7 has its gate electrode connected to a word line 9. The field effect transistor 7 connected to the capacitor 8 has its source/drain electrode connected to a bit line 10. During data writing, a predetermined potential is applied to the word line 9, so that the field effect transistor 7 is turned on and charges applied to the bit line 10 are stored in the capacitor 8. On the other hand, during data reading, a predetermined potential is applied to the word line 9. The field effect transistor 7 is thereby turned on and the charges stored in the capacitor 8 are taken out via bit line 10.
FIG. 7 is a plan view showing a conventional semiconductor memory device provided with a groove type capacitor memory cell, and FIG. 8 is a cross-sectional view taken along line VIII to VIII in FIG. 7.
Referring to these figures, an insulating film for element-to-element isolation 12 is formed on the main surface of a semiconductor substrate 11 for isolating active regions 21. A gate electrode 14, corresponding to the word line 9, is formed on the main surface of the semiconductor substrate 11 with a gate film 13 in-between. The gate electrode 14 is formed by a polycrystal silicon. Source/drain regions 17, and 18 are formed on both sides of the gate electrode 14 on the main surface of the semiconductor substrate 11. A groove 15 is formed on the main surface of the semiconductor substrate 11. A storage node is formed on the inner wall surface of the groove 15. The storage node 16 is an electrically conductive region formed by introducing the impurity ions and dispersing them into the inner wall surface of the groove 15. The storage node 16 and the source/drain region 17 are electrically connected to each other via a connecting impurity-diffusion layer 19 formed on the main surface of the semiconductor substrate 11.
A capacitor insulating film 20 is provided to cover the inner wall surface of the groove 15. This one end of the capacitor insulating film 20 is extended to overlie the insulating film for element-to-element isolation 12. A cell plate 22 is provided to cover the capacitor insulating film 20. The cell plate 22 is partially buried in the groove 15.
An interlayer insulating film 23 is provided on the overall surface of the semiconductor substrate 11 inclusive of the gate electrode 14 and the cell plate 22. A contact hole 24 is formed in the interlayer insulating film 23. A bit line 25 is connected to the source/drain region 18 by way of this control contact hole 24.
In the above described semiconductor memory device, the word line 9 is selected and a predetermined potential is applied to the gate electrode 14 to render the current path between the source/drain regions 17 and 18 conductive to perform the read/write operation.
The method for producing the above described conventional semiconductor memory device provided with the groove type capacitor is hereinafter explained.
Referring to the FIG. 9A, the insulating film for element-to-element separation 12 is formed on the main surface of the semiconductor substrate 11 for isolating on separating an active region from another active region on the main surface of the semiconductor substrate 11. The gate oxide film 13, the gate electrode 14 and an oxide film 26 of the filed effect transistor are then formed on the substrate 11. These films may be produced by sequentially forming a thermal oxide film, polycrystal silicon layer and a CVD SiO.sub.2 film on the substrate 11 and dry etching these thin films by a photolithographic method.
Then, referring to FIG. 9B, N-type impurity ions 27 are introduced in a self-aligning manner towards the main surface of the substrate 11. A first impurity-diffusion region 28 is then formed on both sides of the gate electrode 14 on the main surface of the semiconductor substrate 11.
Then, referring to FIG. 9C, a sidewall spacer 29 is formed on the sidewall of the gate electrode 14.
Then referring to FIG. 9D, a photoresist for etching 30 is formed on the overall surface of the semiconductor substrate 11. The photoresist 30 is then patterned by a photolithographic method for forming a hole of a desired shape above the region where the groove is to be formed. Then, using the patterned photoresist 30 as the mask, the main surface of the semiconductor substrate 11 is subjected to selective etching for forming the groove 15 on the main surface of the semiconductor substrate 11. This selective etching is performed by reactive ion etching under the conditions selected to provide the desired etching selectivity. The photoresist 30 is then removed.
Then, referring to FIG. 9E, N-type impurity ions 27 are introduced into the inner wall surface, inclusive of the lateral and bottom sides, of the groove 15, by rotary ion implantation. After ion implantation, heat treatment is performed for forming a second impurity-diffusion region 31 contiguous to the first impurity diffusion region 28 on the inner wall surface of the groove 15.
Then, referring to FIG. 9F, a nitride film 32 is formed on the overall surface of the semiconductor substrate 11, inclusive of the inner wall surface of the groove 15. After thermal oxidation of the nitride film 32, a polycrystal silicon film 33 is formed on the overall surface of the semiconductor substrate 11, inclusive of the inner surface of the groove 15, and a photoresist for etching 34 is then formed on the polycrystal silicon film 33. The photoresist 34 is then patterned to a desired shape. Then, using this patterned photoresist 34 as the mask, the nitride film 32 and the polycrystal silicon film 33 are patterned by selective etching. In this manner, a capacitor insulating film and a cell plate electrode are formed.
Then, referring to FIG. 9G the interlayer insulating film 23 is heaped or stacked by chemical vapor deposition (CVD) on the overall surface of the semiconductor substrate 11. The contact hole 24 is then formed in the interlayer insulating film 23 and the bit line 10 is connected by way of this contact hole to the first impurity-diffusion region 28 to produce the semiconductor memory device shown in FIG. 8.
Meanwhile, the storage capacity of the above described semiconductor memory device including the groove type capacitor may be increased by increasing the depth of the groove 15 (see FIG. 8).
As an alternative method for increasing the storage capacity of the semiconductor memory device, there is proposed in the art a semiconductor memory device including both the groove type capacitor and the stacked capacitor.
FIG. 10 is a cross-sectional view of a semiconductor memory device including the groove type capacitor and the stacked capacitor, as disclosed in the Japanese Patent Laying-Open No. 190868/1987.
Referring to this figure, a groove 15 is formed on the main surface of the semiconductor substrate 11. A source region 35 and a drain region 36 of a MOS transistor formed around the groove 15 and in the vicinity of the semiconductor substrate surface. A gate electrode 37 is is formed astride the source region 35 and the drain region 36. An impurity-diffusion layer 38 is formed on the inner wall surface of the groove 15 and is connected to the source region 35. A first electrically conductive layer 40 is formed via an insulating film 39 to cover the inner surface of the groove 15. A second electrically conductive layer 42 is formed on the first electrically conductive layer 40 via an insulating layer 41.
In the present semiconductor memory device, the groove type capacitor is formed by the source region 35, impurity-diffusion layer 38, first electrically conductive layer 40, functioning as the cell plate, and the insulating film 39. On this groove type capacitor is formed the stacked capacitor made up of the second electrically conductive layer 42, insulating film 41 and the first electrically conductive layer 40. The groove type capacitor and the stacked capacitor are connected in series with each other to increase the memory cell capacity. The semiconductor memory device including both the groove type capacitor and the stacked capacitor is also disclosed in the Japanese Patent Laying-Open Nos. 248248/1987, 65559/1985, 37962/1987 and 7153/1987.
In the above semiconductor memory device including the groove type capacitor shown in FIG. 8, the depth of the groove 15 need be increased for increasing the capacity of the capacitor. However, increasing the depth of the groove 15 may raise a problem in mass producibility.
On the other hand, in the semiconductor memory device including both the groove type capacitor and the stacked capacitor, shown in FIG. 10, the stacked capacitor must be formed on the previously formed groove type capacitor, so that the high degree of accuracy in registration or position matching between the two types of capacitors is necessitated to raise a problem from the viewpoint of the manufacture process.